Volume 11 Issue 05, September 2023

Review of Design Challenges in Static Random-Access Memory (SRAM) Cell Circuits Based on Low Power Design (LPD)

Hemant Silawat, Shivraj Singh

Page no:01-06


With the proliferation of portable devices in our daily lives, power optimisation has emerged as a primary challenge in modern VLSI technology. Various new gadgets and systems rely heavily on large-scale integration (VLSI) technology. Static random-access memory (SRAM) blocks occupy a significant portion of chip space and are the primary source of leakage power in many contemporary systems. Lowering the supply voltage of SRAM macros has been attempted to reduce power consumption; however, this often leads to increased power dissipation. Due to the growing process-related variations in read and write operation times, achieving stable SRAM cell operation at high power dissipation is increasingly challenging. In this research, we propose a method for scaling the supply voltage of SRAM macros, which effectively reduces overall power dissipation. We present 6T and 10T SRAM circuits that achieve significant power savings during read and write operations while maintaining reasonable performance and stability. Furthermore, the impact of process parameter variations on various design metrics, including read power, write power, leakage power, leakage current, and latency, becomes a critical concern as integration scales up in SRAM cell design. We introduce and compare the proposed 6T and 10T SRAM circuit cells, providing valuable insights into their performance characteristics.