Volume 11 Issue 03, May 2023

Review on Digital Image Watermarking Based on DWT Method and DCT Method

Astha Rani, Aditi Purohit, Rajesh Boghey

Page no:01-05


Digital watermarking has recently gained significant attention as a prominent research topic, thanks to the remarkable advancements in computer and internet technology. Digital watermarking serves as an effective solution to combat illegal copying, modification, and redistribution of multimedia data such as audio, images, and videos. This paper provides a concise overview of different techniques for image watermarking in both the spatial domain and the transform domain. The authors propose a novel digital watermarking algorithm for gray images based on the discrete wavelet transform (DWT), two-dimensional discrete cosine transform (DCT), and singular value decomposition (SVD). The objective is to achieve robust watermarking of digital images to protect digital media copyright efficiently. A comprehensive survey on digital image watermarking is conducted, focusing on hybridising Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) with SVD. While established watermarking algorithms demonstrate their robustness, there is still room for exploration in areas like principal component analysis and redundant and feature extraction-based hybridisation of transforms as alternatives to SVD to enhance performance further. The proposed and existing DCT-based methods are evaluated by comparing their peak signal-to-noise ratio (PSNR) and robustness against various attacks. The paper also discusses different attack scenarios in detail.

RDesign, Implementation, and Performance Analysis of an SRAM Cell for Low-Power Consumption Applications

Sushmita Jain, Naveen Khare

Page no:06-15


SRAM cells play a crucial role in memory designs and find applications in various systems on chips (SoCs). Considering the continuous technological advancements and the need for energy-efficient operation, power dissipation and low power consumption are critical concerns in SRAM cell design. This study proposes a circuit design based on the switching concept to achieve power savings in SRAM cells for low-power consumption applications. The primary objective of the proposed circuit design is to minimise power usage in different devices. As memory cell operation with low voltage consumption gains prominence in low-energy computing, the design of SRAM cells becomes a significant area of research. With its high storage density and quick access time, SRAM has become a vital component in VLSI chips used in notebooks, laptops, IC memory cards, and handheld communication devices. This work explores the write, read, dynamic, and static power consumption and voltage and temperature characteristics of an SRAM circuit for smart applications. Power consumption analysis is a critical criterion in memory design, impacting reading and writing activities. The implemented 6T, 8T, and 10T SRAM cells, along with the proposed circuit design, demonstrate superior efficiency in power usage compared to existing SRAM topologies. By considering different parameters such as write power, read power, and idle time power, the proposed circuit design outperforms the traditional SRAM (6T, 8T, and 10T) circuits. As specifications change with scaling approaches, ensuring SRAM stability becomes crucial for successful low-voltage SRAM design. Simulation results indicate that the proposed design enables faster read operations and optimises the total power delay product. While addressing the read disruption problem encountered in conventional SRAM cells, our primary goal is to reduce power consumption and improve read and write delay performance, as these factors significantly impact memory cell performance.